vibe-ic

Synthesize RTL to gate-level netlist using Yosys. Returns cell count, area, and writes netlist file.

Run Verilator lint on RTL files. Returns warnings and errors. v0.99.2 adds a `strictness` selector — default 'error_only' lets stylistic warnings through (matching Quartus / Icarus tolerance), 'warnings_as_errors' restores the historical -Wall behaviour.

Compile and run RTL simulation using Icarus Verilog. Returns PASS/FAIL. v0.99.3 adds `work_dir` so $readmemh / $readmemb / $fopen / `include resolve relative paths the way the testbench expects (default: dirname of the first source file).

Run formal verification using SymbiYosys. Writes .sby config and runs proof.

Run OpenROAD place & route on a synthesized netlist. Optionally runs CTS + detailed_route + writes routed netlist. Returns area, utilization, timing slack.

Generate GDS file by merging cell GDS library from PDK with routed DEF in a single call. Reads cell GDS first, then overlays DEF placement/routing, writes merged output GDS.

Run static timing analysis on a placed design using OpenSTA (via OpenROAD).

Run LVS. Two modes: (a) `netgen` compares extracted layout SPICE netlist against schematic SPICE — needs foundry netgen setup tcl, currently gf180/sky130 only; (b) `yosys_equiv` (since v0.1.12) compares two structural Verilog netlists (e.g. synth.v vs post-PnR routed.v) using Yosys equiv_simple+equi…

Run DRC using KLayout. For gf180/sky130 uses foundry decks; for custom PDK auto-derives WIDTH/SPACING rules from the tech LEF (or uses an explicit custom_drc_script).

Analyze IR drop on power grid using OpenROAD PSM (Power Grid Analysis). v0.76 adds custom PDK support and via-resistance fallback.

Run equivalence check (LEC) between RTL and gate-level netlist using Yosys.

Run SPICE simulation using ngspice. For analog circuit analysis.

Generate SPICE netlist from xschem schematic (.sch). Batch mode — no GUI needed. v0.108: analog design pipeline.

Run multi-corner PVT SPICE sweep with automated .meas extraction and yield table. v0.108: analog design pipeline. Runs one ngspice invocation per corner×temp combination, aggregates results into a JSON yield matrix.

Run full DFT flow using Fault: scan chain insertion + ATPG + optional JTAG TAP. Returns coverage percentage and test vector count. v2.5.0: pdk=custom supported via custom_dff_names + custom_lib + custom_cell_verilog.

Search the IC Knowledge Base for reference ICs by function, interface, voltage, or natural language. Returns matching ICs with parameters and datasheet URLs. Use when the user describes an IC they want to design and needs to find similar existing ICs.

Run multi-corner STA (SS/TT/FF) on synthesized netlist using OpenSTA. Reports WNS/TNS per corner and overall PASS/FAIL.

Run vibe-ic-d deterministic audit programs against RTL files. Returns per-program PASS/FAIL and findings count.

Prove RTL conforms to its spec contract: port (name/dir/width), reset mode+polarity, and output latency. Spec may be a natural-language prompt, a markdown module header, or a JSON contract. Returns PASS/FAIL + findings.

Lint a spec/prompt for SELF-contradiction before any RTL exists: garbled numbered-port gaps (body references Y2/Y4 absent from a declared Y1/Y3 interface) and reset-semantics contradictions (spec asserts both sync+async, or both active-high+low). Spec may be a natural-language prompt, markdown heade…

Deterministically generate synthesizable FSM RTL from a structured state-transition table (Moore comb/seq or Mealy). Program-first: same spec → byte-identical RTL, no LLM. Spec is a JSON/YAML file with module, kind, encoding, transitions, outputs (+ clk/reset for sequential).

Deterministically generate combinational RTL from a structured truth table (inputs/outputs/rows + default). Program-first: same spec → byte-identical RTL, no LLM, no don't-care guessing. Spec is a JSON/YAML file; `in`/`out` are MSB-first binary strings over the declared ports.

Deterministically generate combinational RTL from a gate netlist (inputs/outputs/wires/gates). Program-first: one assign per gate, byte-identical per spec, no LLM. Ops: and/or/nand/nor/xor/xnor/not/buf.

Deterministically generate combinational RTL for a vector op: reverse (bit/byte/chunk), split, concat, sign_extend, zero_extend. Program-first: one assign, byte-identical per spec, no LLM.

Phase-2 program-first router: auto-classify a structured spec and route to the matching DETERMINISTIC RTL generator (gate-netlist via `gates`, FSM-table via `transitions`, truth-table via `rows`, vector-op via `op`). Returns RTL when deterministic, or fallback:'llm' when no generator applies.

Generate a PROFESSIONAL, high-coverage cocotb testbench deterministically from a project's Phase-1 L-docs: interface (L1/L9), clock/reset (L8/L9), a reference model (closed-form for arithmetic primitives; a bounded-latency + bit-order STREAMING scoreboard that closes the serial-datapath functional-v…

Run cocotb Python testbench with Verilator or Icarus Verilog backend. Returns test pass/fail counts.

Compile design for Intel FPGA (Quartus) or Xilinx (Vivado). Runs on host, not Docker.

Extract parasitics from layout using Magic. Produces SPEF or SPICE extracted netlist. since v0.2.33 (ORGANIC-20260531): set `promote_ports`=true (a.k.a. port_makeall) to inject `port makeall` into the extraction TCL so the emitted `.subckt <top>_flat` carries TOP-LEVEL PORTS — required for device-le…

Extract plain text + structured JSON from vendor docs (.doc / .docx / .pdf / .ppt / .pptx / .xls / .xlsx / .txt / .html) for downstream Phase 1 / spec-derivation skills. v2.6.4: doc_extract.py now emits per-file coverage_score (text_chars / file_size_bytes) into INDEX.json, so the plugin gate binary…

Pre-flight health check. Verifies docker socket, container, every tool binary, and (optionally) a custom PDK. Returns a structured diagnosis with actionable hints. Run this BEFORE any other eda_* call when starting work in a new environment.

Escape hatch — run an arbitrary TCL/script in a backend (openroad / yosys / klayout-python / netgen / magic / ngspice). Use when stock eda_pnr / eda_synth / eda_drc_klayout don't expose the option you need. The agent supplies the full script content; the server pipes it to the backend in the IIC-OSI…

Validate a PDK before using it for synth/PnR. Checks Liberty syntax, LEF tech vs cell consistency, GDS-LEF cell-name match, RESISTANCE PER CUT presence (needed for IR drop), and CTS buffer cell access-point reachability. Saves hours of debugging when bringing up a new foundry deck.

[PLANNER ONLY in v2.5.x] Declarative pipeline planner. Takes a JSON spec of MCP tool calls and emits a timeline manifest enumerating each step — does NOT actually invoke the tools (the MCP server can't reflectively call its own tools yet). The calling agent reads the manifest and dispatches each ste…

Elaborate a SpinalHDL/sbt project to Verilog by running `sbt runMain <main_class>` inside the vibeic-eda container (OpenJDK 17 + sbt present; SpinalHDL pulled from Maven Central, cached). Unblocks Scala-source-only cores like VexRiscv/Murax. Returns success, generated .v files (sha256 + line counts)…