eda-agent

Discover tools by category / maturity / interaction without loading every schema.

Invoke any registered tool by name: the companion to `tool_catalog`.

Check if Altium Designer is running and get status information.

Where you are, in one call. Run this before anything else.

Connect to a running Altium Designer instance.

Flush every dirty Altium document to disk.

Close a transaction a crashed handler left open in Altium.

Snapshot the focused project so the session is revertible.

List saved checkpoints for the current workspace, newest first.

Restore the focused project's files from a checkpoint.

Stop the Altium MCP polling loop. CALL THIS WHEN YOU'RE FINISHED.

Test if the Altium script is responding and report script version.

Report the health of the MCP bridge, workspace, and Altium link.

Create a new blank document of a given kind and save it to disk.

List all documents known to the current Altium workspace.

Diagnostic: enumerate workspace files via Altium's FindFiles helper.

Get information about the currently active (focused) document.

Set a specific document as the active (focused) document.

Get the version of Altium Designer.

Get key Altium Designer preferences.

Dispatch a menu command by path. DISPATCH IS NOT EXECUTION.

Tell the dashboard what high-level task the agent is working on.

Get text content from the Windows clipboard.

Find nets where the maximum and minimum track widths differ by more than 2×.

Find pairs of same-net tracks meeting at < 90° interior angle.

Find SCH component parameters containing obvious "I'll fix this later" placeholder strings that escaped a release.

Find schematic power-port markers (GND, VCC, +3V3 etc.) sitting off-wire.

Find schematic net labels whose location is NOT on any wire or bus.

Find net labels that silently merge, short, or do nothing.

Find schematic components with a VISIBLE supplier-PN parameter.

Find placed components whose internal primitives are NOT locked. Unlocked primitives are a silent fab-bug class -- a stray click + drag in the PCB editor moves a single pad off-center within the footprint without any warning. The gerbers look fine, just slightly off, and the part doesn't solder prop…

Find free-floating PCB text (eTextObject) that's mirrored on the wrong overlay.

Find PCB silkscreens where designators face BOTH 0 and 180 (or both 90 and 270) -- the assembly-readability check.

Find schematic images that are NOT embedded -- they hold only a path reference to the original file.

Find nets that have EXACTLY ONE pin AND at least one net-label / port / power-object on them.

Find groups of ICs with the same (lib_ref, comment) but DIFFERENT Manufacturer Part Numbers.

Find ICs (designator U*) with no fetchable datasheet URL in any of their parameters.

Find IC pins whose NAME looks like a power / ground pin but whose connected NET is not actually a power / ground rail.

Find ICs whose power pins lack a nearby decoupling cap.

Find IC pins with an empty / unset net (excluding pins intentionally named NC / DNC / RSVD / RESERVED).

Check that every placed component shows the parameters its class requires for a legible schematic and a procurable BOM.

Check that schematic power-symbol orientations follow the standard convention so reviewers' eyes can scan the sheet quickly.

Count tented vs untented via SURFACES on the active board and report the tented ratio.

Find schematic ports that aren't actually connected to anything.

Find PCB tracks / arcs with endpoints that are close to another same-net primitive but don't actually touch.

Find signal vias that have no nearby ground / power via for return-current flow.

Find PCB pads / vias closer than ``clearance_mils`` to the board outline (depaneling damage hazard).

Find PCB components whose origin sits outside the board outline.

Find schematic components placed off the snap grid.

Find pads / vias whose copper annular ring has been removed on layers where it's still needed.

Find schematic components that share a designator across sheets.

Find vias connected on only one layer (resonating stubs).

Find schematic nets with port-direction mismatches across sheets.

List components marked Not Fitted in the project's CURRENT variant.

Find PCB polygon regions whose area is zero or unset.

Characteristic impedance of a PCB trace (IPC-2141 / Wadell).

Trace width (mils) to hit a target impedance for a geometry (microstrip / stripline / their *_diff variants). Differential targets need spacing_mils. Inverse of the IPC-2141 impedance formula.

Assess whether a net is electrically long for its edge rate and, if so, recommend a termination (series for point-to-point, Thevenin / parallel for a multi-load bus) with E24 values.

Resolve the effective Er and a match tolerance from a skew budget (or match_fraction * rise_time_ns), then optionally report a group of net lengths against it.

Size a thermal-via field for a target thermal resistance (given directly, or as power_w with a delta_t_c budget), or score an existing via_count. Fourier conduction, R = L/(k*A).

Minimum track width (mils) to carry a current at a temperature rise (IPC-2221), widened by ``margin`` and snapped to a 0.1 mil grid.

Forward IPC-2221: the current a track of this width sustains at a given temperature rise.

Read the design discipline + DesignPlan JSON schema.

Open a durable design-session journal for an autonomous run.

Append one event to a design-session journal.

Read a design session's derived state (stage map, artifacts, ...).

Resume a design run: state plus a plain-language next-action hint.

Decide the single next action for an autonomous design run.

The autonomous spec-to-board loop protocol, in one call.

Start a long engine run as a background job; returns its id.

Status of a background job (or all jobs if ``job_id`` is blank).

Fetch a finished job's result payload (None until it's done).

Open a list of SchLib files and return what components live in them.

Validate a candidate DesignPlan JSON against the schema + cross-check.

List the canonical circuit blocks and their parameter contracts.

Fold a canonical circuit block into a DesignPlan in one call.

Add one part and wire its pins to named nets, in one call.

Wire a parallel bus across two+ parts in one call.

Apply many authoring operations to a plan in ONE call.

Derive the bill of materials from a plan's parts in one call.

Edit an existing plan -- the MODIFY complement to the add tools.

Compute a manufacturable component value, snapped to an E-series.

Report the electrical behaviour of each recognised sub-circuit.

Recommend a controlled-impedance trace width for every differential pair in a plan.

Offline FALLBACK review of a .SchDoc/.PrjPcb: OFF by default.

Reconstruct a .SchDoc's netlist geometrically: OFF by default.

Consolidated BOM from a .SchDoc/.PrjPcb on disk: OFF by default.

One-call offline pre-flight: bundle every plan-level analysis.

Compute a full schematic layout for a DesignPlan, as pure data.

Suggest how to split a design into balanced functional groups.

Instantiate a DesignPlan in Altium.

Capture your placement edits as training data.

Render a DesignPlan to SVG without emitting to Altium.

Structured visual/layout audit of the active schematic.

ERC + connectivity sanity report on the focused project.

Validate a structured DesignRequirement before planning starts.

Validate a fab capability profile and echo the normalized form.

Synthesize PCB design rules + stackup ops from a fab profile.

Propose a multi-sheet hierarchy for a dense DesignPlan.

Rewrite a DesignPlan onto the sheets a hierarchy proposes.